ASIC Verification Engineer / Senior Engineer
Our client SeviTech Systems is looking for an ASIC Verification Engineer / Senior Engineer!
Job Designation: FPGA RTL Design Engineer.
Job Location: Bangalore
Job Type: Permanent
About our Client: http://sevitechsystems.com/
SeviTech is an ASIC design company specializing in ASIC/SOC & FPGA services and solutions. With 14+ years’ experience in the leading semiconductor companies, they bring a unique model of operation with their own Research and Development team who are working constantly on the development of the products. SeviTech Systems is enabling their employees in developing some of the leading, cutting edge solutions with enthusiasm on quality and schedule.
Job description:
• You will be part of an IP or SoC Verification Team leading to first pass Silicon success.
• You will be responsible for driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
• You will be responsible for analyzing Code Coverage, Functional Coverage and Assertions.
• Use industry standard tool, methodologies and HVLs.
Desired Skills and Experience:
• B. Tech. or M. Tech. with 5-8 years of solid experience in verification of complex IPs or SoCs.
• Expertise in Soc Verification using C and SV/UVM or IP Verification using SV/UVM.
• Expertise in AMBA protocols like AXI/AHB/APB and experience in working with ARM Processors.
• Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional Coverage and Assertions.
• Verification experience in any of the protocols like USB/PCIe/DDR or other complex protocols is highly desirable.
• Good knowledge in gate-level simulation, and Scripting languages like Perl, TCL.
• Excellent debugging and problem solving skills.
• Experience in Low Power Verification is a plus.
Qualifications
M. Tech. / B. Tech.
Additional Information
This is an Immediate Opportunity; candidates with less than one month notice will be preferred. Please ignore this post if the above profile doesn’t match with your current Job Role.