Unconventional, Inc.

Member of Technical Staff - SOC Design Lead

Unconventional, Inc. Palo Alto, CA I US Remote 6 days ago
design

About Unconventional

Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand for computation - a demand that is now fundamentally limited by energy, not just in the datacenter, but at a global scale.

At Unconventional, our mission is to solve this. We are rethinking computing from the ground up to build a new foundation for AI that is 1000x more efficient. We're doing this by exploiting the rich physics of semiconductors, mapping neural networks directly to the device physics rather than relying on layers of inefficient abstraction.

The Role

As a Member of Technical Staff, SOC Design Lead, you will be a foundational member of our small, multi-disciplinary R&D team. We are looking for accomplished and highly motivated individuals with a deep understanding of SOC design who are excited to tackle the hardest, most ambiguous technical challenges at the intersection of AI, physics, and computer architecture. You will be responsible for driving invention, prototyping, and validation of the core components of our novel computing platform.

Responsibilities

  • SoC Architecture & Design:
    • Lead the detailed micro-architecture definition and top-level integration of digital blocks, including CPU, memory subsystems, and interfaces.
    • Serve as the technical owner for the integration of third-party IP into the main SoC fabric.
  • Technical Leadership & Mentoring:
    • Provide technical guidance and mentorship to junior and senior digital design and verification engineers.
    • Contribute to setting best practices for design methodologies, code reviews, and quality assurance processes.
  • Hands-on RTL Implementation:
    • Drive and perform hands-on RTL design for complex, timing-critical SoC blocks and digital interfaces, ensuring power, performance, and area (PPA) targets are met.
    • Implement and debug key digital interfaces
  • Design Verification (DV) Leadership:
    • Define and lead the comprehensive SoC-level verification strategy and plan.
    • Oversee and actively participate in the development of a robust verification environment to ensure functional correctness and coverage closure.
    • Triage and debug complex simulation and emulation failures.
  • External Partner Management:
    • Act as the primary technical interface with 3rd party ASIC design and consulting services.
    • Define clear Statements of Work (SOWs), manage technical execution, and ensure timely delivery and quality of contracted IP/blocks.
    • Facilitate seamless hand-off between internal design and external physical implementation (synthesis, timing closure).

Minimum Qualifications

  • Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
  • Experience: 10+ years of industry experience in digital ASIC/SoC design, with at least 2+ years in a technical lead or architect role leading to successful tapeouts and product delivery. Experience working in modern process nodes (22nm, 12nm and newer).
  • Deep Technical Expertise:
    • Expertise in Verilog RTL coding and digital design fundamentals.
    • Proven experience leading or significantly contributing to a large SoC-level verification effort.
  • Design Flow Proficiency:
    • Familiarity with standard EDA tools for simulation, synthesis, linting, and clock domain crossing (CDC) analysis
    • Understanding of the full ASIC design flow, from specification to tape-out.
  • Communication: Excellent written and verbal communication skills, with a track record of successfully managing and collaborating with external vendors or design houses.

Preferred Qualifications (Nice to Have)

  • Experience with design constraints or architectures related to Machine Learning/Neural Network accelerators is a strong plus.
  • Experience integrating large analog mixed-signal blocks into larger subsystems.

Why Join Us?

  • The Mission: Redefine computing for the next 50 years by solving the fundamental energy limitation of AI at a global scale.
  • The Impact: Shape the company's future as a foundational team member. Enjoy massive ownership and an outsized opportunity to drive change.
  • The Challenge: Dive into deeply complex, intellectually stimulating, and unsolved problems at the cutting edge of multiple, converging fields.
  • The Perks: A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

 

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