Senior Hardware Design Engineer, Ethernet Switching

Who You’ll Work With

Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability.

What You'll Do

Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for the end-to-end design and development of advanced hardware solutions that meet the demands of modern networking environments.

Candidates for this position would be responsible for the entire hardware design process:

• Authoring Functional Specifications of high power and high density Ethernet switches used in AI networks
• Selecting and Qualifying Components
• Schematic Capture (both flat and hierarchical)
• Working closely with eCAD teams on PCB layout and component footprints
• Working with internal teams to run (or run your own) signal integrity simulations on both power and datapath signals
• Specifying PCB stackup and fabrication details with various PCB vendors
• Working closely with local and overseas Contract Manufacturers (CM), from proto through production
• Lab bring up and debug of prototypes
• Driving complex system debug between software, hardware, and test teams
• Training CM for high yield test and manufacturing
• Guiding groups of engineers and mentoring younger engineers

Qualifications

• BSEE or MSEE
• 10+ years of relevant experience in hardware engineering
• Experience designing Networking Hardware, particularly involving 100G and 200G PAM4 Ethernet switching
• Embedded x86/ARM system design is highly desirable
• Experience designing 20+ layer count boards featuring 50G+ signals, and advanced PCB manufacturing technologies such as sequential lamination, HDI, and ultra-low-loss materials
• Experience working with multi-phase DC/DC’s for high current, high transient loads
• Experience working with High speed interfaces, such as DDR, PCIe
• Writing specifications and drawing schematics for high complexity boards
• Working closely with CAD designers on complicated layout and routing
• Working closely with Software and test engineers to bring-up and debug systems
• Familiarity with signal integrity and power integrity concepts and tools, such as: impedance, PDN’s, differential routing, insertion loss, S-parameters, TDR’s, VNA’s
• Experience with mass production Design for Manufacturability (DFM)
• FPGA design and system simulation using Verilog
• Working with Contract Manufacturers
• Successfully taking products from concept to production

Compensation Information:

The new hire base pay for this role has a pay range of $130,000 to $225,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The pay range provided reflects base pay only and in addition certain roles may also be eligible for discretionary Arista bonuses and equity. Employees in Sales roles are eligible to participate in Arista’s Sales Incentive Plan, which pays commissions calculated as a percentage of eligible sales. US-based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

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Additional Information

Arista Networks is an equal opportunity employer.  Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law.  All your information will be kept confidential according to EEO guidelines.