Senior Staff DFT MBIST Engineer
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
Location:
Hybrid, working onsite at our Bengaluru, Karnataka, headquarters 3-5 days per week.
Senior Staff DFT MBIST Engineer
D-Matrix is searching for an experienced DFX Engineer to join the fast-growing DFT design team. You will be responsible for defining, specifying, and implementing current and future DFX solutions for AI Accelerators SoCs. We’re revolutionizing AI acceleration with Digital In-Memory Computing (DIMC) and heterogeneous chiplet architectures, delivering unprecedented efficiency for data centers and large language models (LLMs). As a Series B startup backed by industry giants, we combine the agility of a disruptor with the technical ambition of a market leader.
Join a dynamic team and give a boost to your personal career in a challenging and fascinating ever-growing, never-boring area! We look forward to welcoming you to the team!
Your Responsibilities Will Include:
Partitioning for ATPG and hierarchical approaches
ATPG compression and serialization
RTL-Scan insertion and design rule fixing
Expertise in Memory BIST including Memory Repair, In-System Test (IST) for Memories from Implementation to Verification and Silicon Debug
Experience on Boundary Scan and writing DFT mode constraints for IP’s and providing the timing feedback to STA team for DFT modes
Experience on DFT RTL generation and Integration with RTL level QC checks like Spyglass LINT, Spyglass DFT and Fishtail
Familiar with IEEE1149.1, IEEE1500 and IEEE1687 standards
Performing ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations
Conducting in-depth knowledge and hands-on experience in ATPG coverage analysis
Working with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE
Being responsible for diagnostic tool generation for ATPG, MBIST, and bring-up on ATE
Having experience with state-of-the-art, industry-standard DFT tools
Being hands-on from the "nitty-gritty" details to high-level planning
Minimum Qualifications:
BE / ME (or similar) in Electronic Engineering, Computer Science, Computer Engineering, or a related field
7+ years of experience with DFT technologies, including scan test and MBIST
Experience with a hardware description language such as Verilog, System Verilog, or VHDL
Experience with one or more scripting or programming languages (e.g., Perl, Python, TCL, C, etc.)
Ability to work well in a diverse team environment
Experience delivering detailed technical documentation
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.