Automotive Functional Safety Architect – SoC/AI Silicon
About Us
Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.
In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.
We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.
Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Are you up for the challenge?
Position Overview
We are looking for an Automotive Functional Safety Architect – Silicon (SoC/NPU/AI Accelerators) to define and lead the safety architecture of our automotive-grade AI chips.
This is a critical technical leadership role focused on semiconductor-level functional safety. You will design and implement safety strategies compliant with ISO 26262, SOTIF, and ISO/SAE 21434, ensuring our NPUs, CPUs, and SoCs meet the highest standards of automotive safety and reliability.
You will also serve as the technical lead in external engagements, including with automotive partners, customers, and European consortia, representing Axelera AI’s functional safety strategy and driving alignment on safety requirements across the ecosystem.
Important: This role requires hands-on experience with functional safety at the silicon level—not at the vehicle, ECU, or system level. You’ll be working directly with hardware and RTL teams to embed fault-tolerant, safety-compliant features deep into the design.
Key responsibilities:
Functional Safety Architecture: Define and own the ISO 26262-compliant safety architecture for AI-enabled SoCs (ASIL B to D), with a focus on chip-level implementation.
Hardware Safety Design: Work with RTL and SoC architects to integrate fault-tolerant safety mechanisms, including ECC, lockstep, BIST, watchdogs, and other diagnostic features.
Safety Analysis: Lead HARA, FMEDA, FTA, and DFA across hardware and system levels to support robust diagnostic coverage and compliance.
Safety Concepts: Develop and validate technical and functional safety concepts, including requirements allocation, safety goals, and system-level safety paths.
Cross-Functional Collaboration: Partner with internal hardware, software, and systems teams to ensure that safety requirements are implemented and validated across the stack.
External Leadership: Act as technical lead in partner and customer engagements, including participation in European automotive consortia, ensuring alignment of external requirements with internal safety strategy.
Certification Process: Support external audits and liaise with certification bodies for ISO 26262 and SOTIF compliance.
Cybersecurity & SOTIF Integration: Incorporate ISO/SAE 21434 and ISO/PAS 21448 (SOTIF) standards into architecture and development, particularly for AI/ML-based systems.
Safety Documentation: Contribute to and review the safety case, safety plan, safety manual, and traceability artifacts.
Process & Tooling Improvement: Help define and enhance internal safety development processes, methodologies, and tooling infrastructure.
Qualifications
Required:
5+ years of experience in semiconductor functional safety, specifically within ISO 26262-compliant silicon development (ASIL B–D).
Strong hands-on expertise in hardware-level safety architecture, RTL fault detection, and diagnostic mechanism design.
Proficiency in safety analysis methods such as FMEDA, HARA, FTA, and DFA.
Experience interacting with functional safety assessors and certification bodies.
Familiarity with SoC design workflows, verification flows, and embedded safety IP.
Strong communication skills to lead external technical discussions with partners, customers, and auditors.
Preferred:
Experience with NPU/AI accelerator architectures or high-performance computing silicon.
Working knowledge of ISO/SAE 21434 (cybersecurity) and SOTIF (ISO/PAS 21448).
Background in AI/ML-based automotive applications (e.g., perception, autonomous systems).
Experience using safety tooling such as Medini Analyze, Ansys, or proprietary FMEDA tools.
Participation in industry consortia or regulatory working groups.
Location
This position will be preferably based in Bavaria, Germany (hybrid from Munich in the future), with a possibility of fully remote set up + sporadic European travel involved.
What we offer
This is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.
An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.
At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.