Design Verification Engineer

Job Title: Design Verification Engineer
Location: Santa Clara, CA
Duration: 06 months (High Possibility of an extension)

Job Description:
Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:
1.    PCIE verification background
2.    400G MAC verification background

Additional Information

All your information will be kept confidential according to EEO guidelines.