Head of Physical Design
About Etched
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
We’re looking for a Head of Physical Design to lead the end-to-end RTL-to-GDSII path for our next-generation transformer inference ASICs. You’ll own all aspects of physical implementation — from floorplanning and synthesis through P&R and signoff — and lead a world-class team of PD engineers to deliver first-pass silicon that’s fast, reliable, and production-ready. This is a rare opportunity to shape the physical design strategy at a company where timing to market and uncompromising performance are critical to success.
Key Responsibilities
Own and optimize all facets of physical design, including floorplanning, placement, CTS, routing, and timing closure for complex AI accelerators
Build and lead a high-performing PD team, including engineers focused on implementation, flows, and signoff
Define and drive physical signoff strategy, ensuring DRC, LVS, ERC, and CDC are achieved with margin
Partner closely with RTL, DV, backend, and methodologies teams to ensure seamless integration and handoff across the stack
Guide block-level and chip-level floorplanning with input on timing budgets, power domains, and interconnect strategy
Drive early architecture and microarchitecture input to reduce rework and enable schedule predictability
Interface with EDA vendors and the foundry to integrate cutting-edge tools, flows, and node-specific optimizations
Lead the development of automation scripts (e.g., Python, Tcl) to accelerate design cycles and increase flow robustness
Create telemetry and dashboards to track design health and ensure accurate KPIs across closure milestones
Deliver fast, production-grade silicon through aggressive, high-confidence planning and execution
You may be a good fit if you have
10+ years of experience in physical design for advanced-node ASICs, including multiple successful tapeouts
Demonstrated ownership of complex block- and full-chip physical implementation projects, from RTL handoff to signoff
Deep expertise in timing closure, including STA, path analysis, constraint management, and ECO optimization
Experience managing and mentoring physical design teams, ideally in fast-paced or startup environments
Strong scripting and automation skills (Python, Tcl) to optimize workflows and improve engineering velocity
Familiarity with leading EDA tools like Cadence Innovus, Synopsys ICC2, and Mentor Calibre
Comfort working in a high-performance, in-person engineering culture that values ambition and execution
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.