Lead Physical Design Engineer

Efficient is seeking a Physical Design Lead  to join our newly formed hardware engineering organization. The ideal candidate would drive overall physical design convergence of IPs and complete SOC. Provide technical leadership from a PD perspective and help hire and guide the PD team to converge all aspects of Efficients processor designs. The PD lead will wear multiple hats and will also drive the PNR methodology (Floorplanning, Placement, Clock tree design, Routing and Low Power Design) hands on. We believe in a correct-by-construction philosophy and place a great emphasis on ensuring PNR flows accurately model signoff considerations. The PD lead will ensure that we have methodologies in place to ensure the design built considers the right tradeoff between timing and power and optimizes for both aspects. The role is cross functional and we are an integrated highly interdisciplinary team of world class engineers working on an integrated hardware/software co-design based energy efficient processor.

This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Drive and develop PNR flows and methodology for the industry defining Energy efficient general purpose processors.
• Ensure PNR flows accurately model all aspects of PPA and correlate well to timing/power/physical signoff aspects to enable highly optimized and correct by construction design enabling tight and quick design loops and design convergence
• Develop recipes to improve PPA.
• Design Clocks with the best perf/power tradeoffs.
• Develop utils to design power grids in modular fashion.
• Enable design space exploration during different phases of PNR to achieve best in class PPA.
• Develop flows for rapid uarch prototyping in conjunction with RTL
• Develop power aware PNR flows.
• Continuously work on improving flow consistency and efficiency in the context of multiple product lines.
• Develop a strong understanding of the Efficient microarchitecture and how the sw compiler is tightly integrated to the hardware arch. Use this know how to ensure we have the most optimal design from a PPA perspective.

Required Qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• Experience with EDA flow using Cadence/Synopsys/Mentor tools for PD flows, like Genus, Innovus and Fusion Compiler.
• Experience with PD signoff flows/tools like tempus/primetime, voltus/redhawk, pegasus/icv, Quantus/starrc.
• Experience with hierarchical design and modelling
• Hands-on experience in convergence of high-frequency and low power designs.
• Knowledge of static timing analysis, Power analysis and multi scenario design and expertise in low power design techniques (isolation, level shifting, power switches..).
• Experience with low power implementation typical in industry,
• Excellent scripting skills in TCL, shell and python.

Desired Qualifications & Experience Requirements

• Experience in design space exploration for maximizing PPA. Doing feasibility level sweeps to figure out optimal design build points.
• Proficiency with industry-grade physical design flow.
• Knowledge of technology fundamentals and its implications to physical design

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.