Power Architect

We are seeking a uniquely skilled Power Architect who can own the full lifecycle of chip power — from early architectural power strategy and modeling through to physical implementation, verification, and silicon sign-off. This role bridges the gap between power architecture decisions made at the system and microarchitecture level and their physical realization in RTL, synthesis, place-and-route, and signoff. It is ideal for someone who understands that power decisions made at the architecture stage have cascading consequences in implementation, and who can drive coherent, optimized outcomes across both domains.

This is a senior technical leadership role with high visibility, requiring deep expertise in low-power design techniques, power-aware physical implementation, and the ability to influence architectural trade-offs and implementation execution simultaneously. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production on mulitple product lines. Join our team and help us shape the future of computing at the edge and beyond!

Key Responsibilities

• Help define the chip-level power architecture — voltage domains, power islands, power modes, state machines, and transition sequencing aligned with product use cases and thermal budgets
• Own the DVFS strategy — defining voltage-frequency operating points, regulator requirements, and software/firmware interfaces for dynamic power management
• Work across teams to author and primarily own the UPF specification as the golden power intent document across the full design cycle from architecture through implementation signoff
• Drive early accurate power modeling and estimation at the architectural level to guide design decisions before RTL is available. Partner with RTL/PD teams to get more accurate data for power model building blocks.
• Guide RTL designers/PD on power-efficient design practices — clock gating strategies, operand isolation, memory shutdown/retention, and activity reduction techniques
• Drive power-aware design flows — ensuring correct insertion of isolation cells, level shifters, retention registers, power switches, and multi-Vt optimization. Vector driven PD build flows and RTL flows to assess and improve power. “You dont improve what you dont measure.”
• Design the power delivery network (PDN) — defining grid topology, metal layer assignment, strap widths, via density, and decoupling strategy for each voltage domain to ensure consistent grid design across the chip ensuring we dont have to jack up power post-si to meet performance goals and jeopardize our power goals.
• Drive IR drop and electromigration analysis and signoff using tools like RedHawk, Voltus across all power modes and workload scenarios
• Define power switch placement and sizing strategy — balancing rush current, wake-up time, voltage droop, and area overhead
• Own chip-level power analysis and budgeting from early RTL estimation through gate-level vectored analysis to final signoff, tracking against targets throughout the design cycle
• Lead power reduction campaigns — identifying dominant contributors and deploying targeted techniques such as Vt swapping, clock gating improvements, and voltage optimization
• Own the power-aware verification strategy — ensuring all power state transitions, isolation, retention, level shifting, and sequencing are thoroughly verified via UPF-driven simulation
• Collaborate with package and thermal teams on power delivery co-design, thermal design power constraints, and hotspot mitigation
• Correlate pre-silicon power estimates with post-silicon measurements and feed learnings back to improve modeling accuracy for future projects
• Serve as the single technical authority on chip power — influencing architectural trade-offs, mentoring engineers, driving EDA flow development, and representing power readiness in tapeout sign-off.

Required Qualifications

• Education: Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field. Bachelor's with exceptional experience considered.
• Experience: 10+ years of progressive experience in IP/SoC design with deep expertise spanning both power architecture and physical implementation. At least 3–5 years in a lead or architect role owning chip-level power strategy.
• Power Architecture: Proven experience defining multi-voltage, multi-power-domain architectures with DVFS, power gating, retention, and dynamic power management for complex SoCs.
• UPF Expertise: Deep hands-on expertise in authoring, debugging, and evolving UPF across the design cycle — from strategic intent through implementation-level detail.
• Power Analysis Tools: Proficiency with industry power analysis and signoff tools — Synopsys PrimePower/PrimeTime PX, Cadence Voltus/Joules, or Ansys RedHawk.
• Physical Implementation: Strong understanding of power grid design, IR drop analysis, EM analysis, power switch implementation, and multi-voltage physical design challenges.
• RTL & Synthesis: Solid Verilog/SystemVerilog skills with the ability to read and review RTL for power efficiency. Experience with power-aware synthesis flows.
• SoC Architecture: Deep understanding of modern SoC architectures — processors, interconnects, memory subsystems, and their power behavior.
• Scripting: Proficiency in Python, Tcl, or Perl for power analysis automation, data post-processing, and flow development.
• Communication: Ability to translate complex power analysis into clear recommendations for architects, designers, and leadership..

Preferred Qualifications

• Experience with advanced node design (7nm, 5nm, 3nm) and the associated power challenges — increased leakage, reduced voltage headroom, FinFET/GAA-specific considerations.
• Background in adaptive voltage scaling, body biasing, or on-chip voltage regulation techniques.
• Experience with power modeling at the system level using tools like Arm Socrates, custom power models, or SystemC-based power estimation.
• Familiarity with embedded power management firmware and software-hardware interfaces for DVFS, ACPI, and PSCI.
• Experience with AI/ML workload power characterization and optimization.
• Background in automotive (ISO 26262), mobile, data center, or high-performance computing power design challenges.
• Experience correlating pre-silicon power estimates with post-silicon measurements and driving modeling accuracy improvements.
• Knowledge of package-level power delivery design (PDN), including VRM selection, decoupling strategies, and package-silicon co-simulation.

We offer a competitive salary for this role, generally ranging from $200,000 to $230,000, along with meaningful equity and comprehensive benefits. The final compensation package will be based on your experience and location, with some flexibility to ensure we align with the right candidate.